Verilog HDL Simulator Technology

ABSTRACT

Digital logic design is becoming increasingly complex in multi-billion transistor VLSI. In order to model such a complex circuit, Verilog has emerged to be one of the most widely used Hardware Description Languages in digital VLSI design. Verilog's ability to model a circuit at different levels makes it a preferred mode of design entry. At every stage in the development, simulations are needed to verify circuit correctness. Various sorts of software and hardware assisted digital logic simulators were developed ever since the adoption of Verilog within the industry. Researchers are actively studying new techniques and approaches to keep simulators relevant. This blog surveys the research activities in Verilog simulator technologies.

What is Verilog Simulation ?

Verilog is a hardware description language and there is no requirement for designers to simulate their RTL designs to be able to convert them into logic gates. So what is the need to simulate?

Simulation is a technique of applying different input stimulus to the design at different times to examine if the RTL code behaves the intended way. Essentially, simulation is a well-followed technique to verify the robustness of the design. It is also the same as how a fabricated chip are going to be utilized in the real world and the way it reacts to different inputs.

For example, the design above represents a positive edge detector with inputs clock and signal which are evaluated at periodic intervals to calculate the output pe as shown. Simulation allows us to look at the timing diagram of related signals to know how the design description in Verilog actually behaves.

There are several EDA companies that develop simulators capable of determining the outputs for various inputs to the design. Verilog is defined in terms of a discrete event execution model and different simulators are free to use different algorithms to produce the user with a uniform set of results. The Verilog code is split into multiple processes and threads and may be evaluated at different times within the course of a simulation, which can be touched upon later.

Free and Open source Simulators

Cascade

Just-in-Time Verilog simulator and compiler for FPGAs allowing to instantly run both synthesizable and unsynthesizable Verilog on hardware

GPL Cver

This is a GPL open-source simulator. It is a pure simulator. This simulator is not fully IEEE 1364-2001 compliant. It does not support generate and constant functions.

Icarus Verilog

Also known as iverilog. Good support for Verilog 2005, including generate statements and constant functions.

LIFTING

LIFTING (LIRMM Fault Simulator) is an open-source simulator able to perform both logic and fault simulation for single/multiple stuck-at faults and single event upset (SEU) on digital circuits described in Verilog.

Verilator

This is a very high speed open-source simulator that compiles synthesizable Verilog to multithreaded C++/SystemC. Testbench code must be written as synthesiable RTL, or as a C++ or SystemC testbench. Verilator does not support behavioral Verilog syntax for writing Testbenches. For example, there is no support for verilog tasks with # and @ operators for generating behavioral testbench driver code.

References

http://www.synopsys.com/Tools/Verification/hardware-verification/emulation/Pages/zebu-server-asic-emulator.aspx
http://www.veripool.org/wiki/veripool/Verilog_Simulator_Benchmarks
http://www.mentor.com/products/fv/emulation-systems
http://www.bawankule.com/verilogcenter/simspeed.html