Verilog HDL Simulator

The design of digital logic is becoming increasingly difficult for many billions of translucent VLSIs. For a model of such a circuit, Verilog turned out to be one of the most widely used Hardware Definitions in VLSI digital architecture. Verilog’s ability to model a circuit at different output levels makes it a preferred method of projecting the design from the concept point to obtaining the final network list. At all stages in development, imitation is absolutely necessary to ensure circuit accuracy. Various types of software and hardware that assist digital logic simulators have been developed since the introduction of Verilog in the industry. With the increase in circuit design and complexity, large retailers of the simulator are struggling to improve simulation in order to maintain the quality and engineering costs of product production. Researchers are keenly interested in developing and developing new simulators. This paper examines the research activities in Verilog simulator technology and compares the strengths and weaknesses of all technologies.

HDL simulation software is also a long way from where it started as a single marketing product offered by one company. Today, simulators are available from many vendors at a variety of prices, including free ones. For desktop / personal use, Aldec, Mentor, LogicSim, SynaptiCAD, TarangEDA and others offer less than US $ 5000 tools on the Windows 2000 / XP platform. The suites integrate the simulator engine with a complete development environment: text editor, waveform viewer, and RTL level browser. In addition, limited Aldec and ModelSim simulator programs are downloaded for free, from OEM partners (Microsemi, Altera, Lattice Semiconductor, Xilinx, etc.) for those who wish open source software, there is Icarus Verilog, GHDL among others.

In addition to the desktop level, enterprise-level simulations offer faster simulation time, stronger language simulation support (VHDL and Verilog), and most importantly, more accurate gate-level simulation (SDF-annotated). The last point is very important in the ASIC tapeout process, where the design database is released in the construction. (Semiconductor Foundries places the use of selected tools on the approved list, so that the customer’s configuration determines the login status. hundreds of entry levels include Cadence Incisive Enterprise Simulator, Mentor ModelSim / SE, and Synopsys VCS. Prices are not publicly published, but all three retailers charge $ 25,000- $ 100,000 USD per seat, a 1 year long-term license.

FPGA vendors do not need expensive business simulators for their design flow. In fact, many retailers are installing the OEM version of a third-party HDL simulator in their design suite. The integrated simulator is taken from the entry or low-level version, and integrated with the FPGA vendor device libraries. For high-volume FPGA projects, an independent simulator is recommended, as the OEM version may not have the capacity or speed to successfully handle large formats.

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